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cy25200 programmable spread spectrum clock generator for emi reduction cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07633 rev. *h revised december 7, 2010 programmable spread spectrum clock generator for emi reduction features wide operating output (ssclk) frequency range ? 3 to 200 mhz programmable spread spectrum with nominal 31.5 khz modulation frequency center spread: 0.25% to 2.5% down spread: ?0.5% to ?5.0% input frequency range ? external crystal: 8 to 30 mhz fundamental crystals ? external reference: 8 to 166 mhz clock integrated phase-locked loop (pll) programmable crystal load capacitor tuning array low cycle-to-cycle jitter 3.3 v operation with 2.5 v output clock drive option spread spectrum on and off function power down or output enable function output frequency select option field-programmable package: 16 pin tssop description the cy25200 is a programmable clock generator with spread spectrum capability. spread s pectrum modulates the output clock frequency over a small range, spreading the energy and reducing the energy peak. this is a powerful technique to reduce emi in a variety of applications. it uses either an external reference clock or a crystal for an input. it also uses a pll to generate a spread spectrum output clock that can be a different frequency than the input. up to six output clocks are available and up to two of them can be refclks (copies of the input clock, without spread). the cy25200 is highly configur able. programmable variables include the input and output frequencies, spread percentage, center spread or down spread, and control pin functions. the oscillator pin capacitance can also be programmed to match the load capacitance requirement (c l )of the crystal, eliminating the need for external capacitors. available features include output enable, power down, spread on/off, frequency select, and the option to power some output clocks at 2.5 v. cypress? web-based cyberclocks online software is used to configure the device. programmability enables fast prototyping, which is particularly useful when doing emc testing and determining the optimal spread settings. divider pll ssclk3 q p vco ? ssclk2 ssclk4 ssclk5/refout/cp2 ssclk6/refout/cp3 bank 1 divider bank 2 output select ssclk1 matrix vddl avss avdd vss vssl vdd cp0 cp1 2 35 13 11 6 410 7 8 9 12 14 15 xin/clkin osc. xout c xin 1 c xout 16 logic block diagram [+] feedback
cy25200 document number: 38-07633 rev. *h page 2 of 15 contents pin configuration ............................................................. 3 general description ......................................................... 3 programming description ............................................... 4 field-programmable cy25200 .................................. 4 cyberclocks ? online software ................................... 4 factory-programmed cy25200 ... ........... ........... ......... 4 product functions ............................................................ 5 control pins (cp0, cp1, cp2 and cp3) ..................... 5 example ...................................................................... 5 clksel ....................................................................... 5 input frequency (xin, pin 1 and xout, pin 16) ......... 5 cxin and cxout (pin 1 and pin 16) ......................... 5 output frequency (ssclk1 through ssclk6 outputs) .................................. 5 spread percentage (ssclk1 to ssclk6 outputs) .... 6 modulation frequency ............ ..................................... 6 switching waveforms ...................................................... 7 informational graphs ....................................................... 8 absolute maximum rating .............................................. 9 recommended crystal specifications ........................... 9 recommended operating conditions ............................ 9 dc electrical specifications ............................................ 9 ac electrical specifications .......................................... 10 ordering information ...................................................... 11 possible configurations ............................................. 11 ordering code definitions ..... .................................... 11 package drawing and dimensions ............................... 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy25200 document number: 38-07633 rev. *h page 3 of 15 pin configuration figure 1. pin diagram general description the cy25200 is a spread spec trum clock generator (sscg) ic used to reduce electro magnetic interference (emi) found in today?s high speed digital electronic systems. the device uses a cypress proprietary phase-locked loop (pll) and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the input clock. by frequency modulating the clock, the measured emi at the fundamental and harmonic frequencies are reduced. this reduction in radiated energy significantly reduces the cost of complying with regulatory agency requirements (emc) and improves time to market, without degrading system performance. the cy25200 uses a factory and field-programmable configuration memory array to synthesize output frequency, spread %, crystal load capacitor, clock control pins, pd#, and oe options. the spread % is factory and field-programmed to either center spread or down spread with various spread percentages. the range for center spread is from 0.25% to 2.50%. the range for down spread is from ?0.5% to ?5.0%. contact the factory for smaller or larger spread % amounts, if required. the input to the cy25200 is either a crystal or a clock signal. the input frequency range for crystals is 8 to 30 mhz and for clock signals is 8 to 166 mhz. the cy25200 has six clock outputs, ssclk1 to ssclk6. the frequency modulated ssclk outputs are programmed from 3 to 200 mhz. the cy25200 products are available in a 16-pin tssop package with a commercial operat ing temperature range of 0 to 70 ? c. note 1. pins are programmed to be any of the following control signals: oe: output enable, oe = 1, all the ssclk outputs are enabled; pd#: power down, pd# = 0, all the ssclk outputs are three-stated and the part enters a low power state; sson: spread spectrum control (sson = 0, no spread and ss on = 1, spread signal), clksel: ssclk output frequency select.see control pins (cp0, cp1, cp2 and cp3) for control pins programming options. table 1. pin summary name pin number description xin 1 crystal input or reference clock input xout 16 crystal output. leave this pin floating if external clock is used vdd 2 3.3 v power supply for digital logic and ssclk5 and 6 clock outputs avdd 3 3.3 v analog?pll power supply vss 13 ground avss 5 analog ground vddl 11 2.5 v or 3.3 v power supp ly for ssclk1/2/3/4 clock outputs vssl 6 vddl power supply ground ssclk1 7 programmable spread spectrum clock output at vddl level (2.5 v or 3.3 v) ssclk2 8 programmable spread spectrum clock output at vddl level (2.5 v or 3.3 v) ssclk3 9 programmable spread spectrum clock output at vddl level (2.5 v or 3.3 v) ssclk4 12 programmable spread spectrum clock output at vddl level (2.5 v or 3.3 v) ssclk5/refout/cp2 14 programmable spread spectrum clock or buffered reference output at vdd level (3.3 v) or control pin, cp2 ssclk6/refout/cp3 15 programmable spread spectrum clock or buffered reference output at vdd level (3.3 v) or control pin, cp3 cp0 [1] 4 control pin 0 cp1 [1] 10 control pin 1 [+] feedback
cy25200 document number: 38-07633 rev. *h page 4 of 15 programming description field-programmable cy25200 the cy25200 is programmed at t he package level, and must be programmed prior to installation on a circuit board. field programmable devices are denoted by an ?f? in the ordering code, and are blank when shipped. the cy25200 is flash technology based, which allows it to be reprogrammed up to 100 times. this allows for fast and easy design changes and product updates, and eliminates issues wit h old and out of date inventory. samples and small prototype quantities are programmed on the cy3672 PROGRAMMER with the cy3695 socket adapter. cyberclocks ? online software cyberclocks ? online software is a web based software application that allows the user to custom configure the cy25200. all the parameters in table 2 and table 3 are entered as variables into the softwa re. cyberclocks online outputs an industry standard jedec file used for programming the cy25200. cyberclocks online is available at www.cyberclocksonline.com website. factory-programmed cy25200 factory programming by cypress is available for high volume orders. all requests must be subm itted to the local cypress field application engineer (fae) or sales representative. after the request is processed, you will receive a new part number, samples, and data sheet with the programmed values. this part number is used for additional sample requests and production orders. table 2. fixed function pins pin function output clock frequency input frequency c xin and c xout spread percent modulation frequency pin name ssclk[1:6] xin and xout xin and xout ssclk[1:6] ssclk[1:6] pin# 7, 8, 9, 12, 14, 15 1 and 16 1 and 16 7, 8, 9, 12, 14, 15 7, 8, 9, 12, 14, 15 units mhz mhz pf % and center- or down-spread khz program value clksel = 0 user specified user specified user specified u ser specified user specified program value clksel = 1 user specified table 3. multi-function pins pin function output clock/refo ut/oe/sson/clksel oe/pd#/sson/clksel pin name ssclk5/refout/cp2 ssclk6/refout/cp3 cp0 cp1 pin# 14 15 4 10 units function function function function user specified user specified u ser specified user specified [+] feedback
cy25200 document number: 38-07633 rev. *h page 5 of 15 product functions control pins (cp0, cp1, cp2 and cp3) four control signals are available through programming of pins 4, 10, 14, and 15. cp0 (pin 4) and cp1 (pin10) are specifically designed to function as control pins. however, pins 14 (ssclk5/refout/cp2) and 15 (ssclk6/refout/cp3) are multi-functional and can be programmed to be either a control signal or an output clock (ssclk or refout). all of t he control pins, cp0, cp1, cp2, and cp3 are programmable to one of the following functions: oe (output enable): if oe = 1, all ssclk and refout outputs are enabled. sson (spread spectrum control) : if sson = 1, spread is on; if sson = 0, spread is off. clksel (clock select): frequency select for all ssclk outputs. pd# (power down; active low): if pd# = 0, all the outputs are three-stated and the part enters a low power state. note that the pd# function is available only on cp0 or cp1; it is not available on cp2 or cp3. example here is an example with three control pins: clkin = 33 mhz ssclk1/2/3/4 = 100 mhz with 1% spread ssclk 5 = refout(33 mhz) cp0 (pin 4) = pd# cp1 (pin 10) = oe cp3 (pin 15) = sson the pinout for the above example is shown in figure 2 . figure 2. example pin diagram clksel the clksel control pin enables you to select between two different ssclk output frequencie s. these must be related frequencies that are derived of f of a common pll frequency. specifically, clksel does not change the pll frequency. it only changes the output divider. for instance, 33.333 mhz and 66.666 mhz are both derived from a pll frequency of 400 mhz, by dividing it down by 12 and 6 respectively. table 4 on page 6 shows an example of how this is implemented. the pll frequency range is 100 to 400 mhz. the two output dividers in the cy25200 can be any integer between 2 and 130, providing two different but related frequencies as explained above. table 4 on page 6 and figure 3 on page 6 show an example configuration using the frequen cies just described. in this example, the configurable pins ssclk5 (pin 14) and ssclk6 (pin 15) are used as output clocks. input frequency (xin, pin 1 and xout, pin 16) the input to the cy25200 is a crystal or a clock. the input frequency range for crystals is 8 to 30 mhz, and for clock signal is 8 to 166 mhz. c xin and c xout (pin 1 and pin 16) the cy25200 has internal load capacitors at pin 1 (c xin ) and pin 16 (c xout ). c xin always equals c xout , and they are programmable from 12 pf to 60 pf, in 0.5 pf increments. this feature eliminates the need for external crystal load capacitors. the following formula is used to calculate the value of c xin and c xout for matching the crystal load (c l ): c xin = c xout = 2c l ? c p where c l is the crystal load capacito r as specified by the crystal manufacturer and c p is the parasitic pcb capacitance on each node of the crystal. for example, if a crystal with c l of 16 pf is used, and c p is 2 pf, c xin and c xout is calculated as: c xin = c xout = (2 16) ? 2 = 30 pf. if using a driven reference clock, set c xin and c xout to the minimum value 12 pf, connect the reference to xin/clkin, and leave xout unconnected. output frequency (ssclk1 through ssclk6 outputs) all the ssclk outputs are produ ced by synthesizing the input reference frequency using a pll and modulating the vco frequency. ssclk[1:4] are fixed function output clocks (ssclk). ssclk5 and ssclk6 are also programmable to function the same as ssclk[1:4], or as buffer ed copies of the input reference (refout), or as control pin as discussed in control pins (cp0, cp1, cp2 and cp3) . to use the 2.5 v output drive option on ssclk[1:4], vddl must be connected to a 2.5 v power supply (ssclk[1:4] outputs are powered by vddl). when using the 2.5 v output drive option, th e maximum output frequency on ssclk[1:4] is 166 mhz. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl oe 100mhz 33.0mhz nc vdd pd# avss 100mhz sson refout(33.0mhz) avdd vddl 100mhz 100mhz [+] feedback
cy25200 document number: 38-07633 rev. *h page 6 of 15 spread percentage (ssclk1 to ssclk6 outputs) the ssclk frequency is programmed to a percentage value from 0.25% to 2.5% for center spread and from ?0.5% to ?5.0% down spread. the granularity is 0.25%. modulation frequency the default modulation frequency is 31.5 khz. other modulation frequencies available via the configuration software are 30.1 khz and 32.9 khz. figure 3. using clock select, clksel control pin configuration pinout table 4. using clock se lect, clksel control pin input frequency (mhz) clksel (pin 4) ssclk1 (pin 7) ssclk2 (pin 8) ssclk3 (pin 9) ssclk4 (pin 12) refout (pin 14) refout (pin 15) 14.318 clksel = 0 33.33 33.33 33.33 33.33 14.318 14.318 clksel = 1 66.66 66.66 66.66 66.66 14.318 14.318 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl sson 33.33/66.66 mhz 14.318 mhz xout vdd clksel avss 33.33/66.66 mhz refout(14.318 mhz) refout(14.318mhz) avdd vddl 33.33/66.66 mhz 33.33/66.66 mhz [+] feedback
cy25200 document number: 38-07633 rev. *h page 7 of 15 switching waveforms figure 4. duty cycle timing (dc = t 1a /t 1b ) figure 5. output rise and fall time (ssclk and refclk) figure 6. power down and power up timing figure 7. output enable and disable timing a output tr v dd 0 v tf output rise time (tr) = (0.6 x v dd )/sr1 (or sr3) output fall time (tf) = (0.6 x v dd )/sr2 (or sr4) refer to ac electrical characteristics table for sr (slew rate) values. ssclk v dd t pu t stp v il v ih power down 0 v (asynchronous ) high impedance ssclk v dd t oe1 v il v ih output enable 0 v (asynchronous ) high impedance t oe2 [+] feedback
cy25200 document number: 38-07633 rev. *h page 8 of 15 informational graphs the informational graphs are meant to convey the typical perform ance levels. no performance spec ifications is implied or guaran teed. spread spectrum profile: fnom=166mhz, fmod=30khz, spread%= -4% 172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5 fnominal 0 20 40 60 80 100 120 140 160 180 200 time (us) spread spectrum profile: fnom=166mhz, fmod=30khz, spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5 spread spectrum profile: fnom=66mhz, fmod=30khz, spread%= -4% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 68.5 68 67.5 67 66.5 66 65.5 65 64.5 6 4 63.5 spread spectrum profile: fnom=66mhz, fmod=30khz, spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 67.5 67 66.5 66 65.5 65 64.5 [+] feedback
cy25200 document number: 38-07633 rev. *h page 9 of 15 absolute maximum rating supply voltage (vdd).... .............. ............ ........ ?0.5 to +7.0 v dc input voltage ................................. ?0.5 v to v dd + 0.5 v storage temperature (non-condensing) ... ?55 ? c to +125 ? c junction temperature .... ............ .............. ?40 ? c to +125 ? c data retention at tj = 125 ? c ...............................> 10 years package power dissipation...................................... 350 mw static discharge voltage......................................... > 2000 v (per mil-std-883, method 3015) recommended crystal specifications parameter description comments min typ max unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut 8?30mhz c lnom nominal load capacitance internal load caps 6 ? 30 pf r 1 equivalent series resistance (esr) fundamental mode ? ? 25 ? r 3 /r 1 ratio of third overtone mode esr to fundamental mode esr ratio used because typical r 1 values are much less than the maximum specification 3?? ? dl crystal drive level no external series resistor assumed ? 0.5 2 mw recommended oper ating conditions parameter description min typ max unit v dd operating voltage 3.135 3.3 3.465 v v ddlhi operating voltage 3.135 3.3 3.465 v v ddllo operating voltage 2.375 2.5 2.625 v t ac ambient commercial temp 0 ? 70 ? c c load maximum load capacitance v dd /v ddl = 3.3 v ? ? 15 pf c load maximum load capacitance v ddl = 2.5 v ? ? 15 pf f ssclk-highvoltage ssclk1/2/3/4/5/6 when v dd = a vdd = v ddl = 3.3 v 3 ? 200 mhz f ssclk-lowvoltage ssclk1/2/3/4 when v dd = a vdd = 3.3 v and v ddl = 2.5 v 3 ? 166 mhz r efout refout when v dd = a vdd = 3.3 v and v ddl = 3.3 v or 2.5 v 8 ? 166 mhz f ref1 clock input 8 ? 166 mhz f ref2 crystal input 8 ? 30 mhz t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms dc electrical specifications parameter [2] name description min typ max unit i oh3.3 output high current v oh = v dd ? 0.5 v, v dd /v ddl = 3.3 v 12 24 ? ma i ol3.3 output low current v ol = 0.5 v, v dd /v ddl = 3.3 v 12 24 ? ma i oh2.5 output high current v oh = v ddl ? 0.5 v, v ddl = 2.5 v 8 16 ? ma i ol2.5 output low current v ol = 0.5 v, v ddl = 2.5 v 8 16 ? ma v ih input high voltage cmos levels, 70% of v dd 0.7 ? 1.0 v dd v il input low voltage cmos levels, 30% of v dd 0?0.3v dd i vdd [3] supply current av dd /v dd current ? ? 33 ma i vddl2.5 [3] supply current v ddl current (v ddl = 2.625 v) ? ? 20 ma i vddl3.3 [3] supply current v ddl current (v ddl = 3.465 v) ? ? 26 ma i dds power down current v dd = v ddl = av dd = 3.465 v ? ? 50 ? a i ohz i olz output leakage v dd = v ddl = av dd = 3.465 v ? ? 10 ? a notes 2. not 100% tested, guaranteed by design. 3. i vdd currents specified for ssclk1/2/3/4/5/6 = 33.33 mhz with clkin = 14.318 mhz and 15 pf on all the output clocks. [+] feedback
cy25200 document number: 38-07633 rev. *h page 10 of 15 ac electrical specifications parameter description condition min typ max unit dc output duty cycle ssclk, measured at v dd /2 45 50 55 % output duty cycle refclk, measured at v dd /2 duty cycle of clkin = 50%. 40 50 60 % sr1 rising/falling edge slew rate ssclk1/2/3/4 < 100 mhz, v dd = v ddl = 3.3 v 0.6 ? 2.0 v/ns sr2 rising/falling edge slew rate ssclk1/2/3/4 ?? 100 mhz, v dd = v ddl = 3.3 v 0.8 ? 3.5 v/ns sr3 rising/falling edge slew rate ssclk1/2/3/4 < 100 mhz, v dd = v ddl = 2.5 v 0.5 ? 2.2 v/ns sr4 rising/falling edge slew rate ssclk1/2/3/4 ?? 100 mhz, v dd = v ddl = 2.5 v 0.6 ? 3.0 v/ns sr5 rising/falling edge slew rate ssclk5/6 < 100 mhz, v dd = v ddl = 3.3 v 0.6 ? 1.9 v/ns sr6 rising/falling edge slew rate ssclk5/6 ?? 100 mhz, v dd = v ddl = 3.3 v 1.0 ? 2.9 v/ns t ccj1 cycle-to-cycle jitter ssclk1/2/3/4 clkin = ssclk1/2/3/4 = 166 mhz, 2% spread and ssclk5/6 = refout, v dd = v ddl = 3.3 v ??110ps clkin = ssclk1/2/3/4 = 66.66 mhz, 2% spread and ssclk5/6 = refout, v dd = v ddl = 3.3 v ? ? 170 ps clkin = ssclk1/2/3/4 = 33.33 mhz, 2% spread and ssclk5/6 = refout, v dd = v ddl = 3.3 v ? ? 140 ps clkin = ssclk1/2/3/4 = 14.318 mhz, 2% spread and ssclk5/6 = refout, v dd = v ddl = 3.3 v ? ? 290 ps t ccj2 cycle-to-cycle jitter ssclk5/6=refout clkin = ssclk1/2/3/4 = 166 mhz, 2% spread and ssclk5/6 = refout, v dd = v ddl = 3.3 v ? ? 100 ps clkin = ssclk1/2/3/4 = 66.66 mhz, 2% spread and ssclk5/6 = refout, v dd = v ddl = 3.3 v ? ? 120 ps clkin = ssclk1/2/3/4 = 33.33 mhz, 2% spread and ssclk5/6 = refout, v dd = v ddl = 3.3 v ? ? 180 ps clkin = ssclk1/2/3/4 = 14.318 mhz, 2% spread and ssclk5/6 = refout, v dd = v ddl = 3.3 v ? ? 180 ps t ccj3 cycle-to-cycle jitter ssclk1/2/3/4 clkin = ssclk1/2/3/4 = 166 mhz, 2% spread and ssclk5/6 = refout, v dd = 3.3 v, v ddl = 2.5 v ??110ps clkin = ssclk1/2/3/4 = 66.66 mhz, 2% spread and ssclk5/6 = refout, v dd = 3.3 v, v ddl = 2.5 v ? ? 170 ps clkin = ssclk1/2/3/4 = 33.33 mhz, 2% spread and ssclk5/6 = refout, v dd = 3.3 v, v ddl = 2.5 v ? ? 190 ps clkin = ssclk1/2/3/4 = 14.318 mhz, 2% spread and ssclk5/6 = refout, v dd = 3.3 v, v ddl = 2.5 v ? ? 330 ps t stp power down time time from falling edge on pd# to stopped outputs (asynchronous) ? 150 300 ns t oe1 output disable time time from falling edge on oe to stopped outputs (asynchronous) ? 150 300 ns t oe2 output enable time time from risi ng edge on oe to outputs at a valid frequency (asynchronous) ? 150 300 ns f mod spread spectrum modulation frequency ssclk1/2/3/4/5/6 30.0 31.5 33.0 khz t pu1 power up time, crystal is used time from rising edge on pd# to outputs at valid frequency (asynchronous) ?35ms t pu2 power up time, reference clock is used time from rising edge on pd# to outputs at valid frequency (asynchronous) ?23ms t skew [4] clock skew output to output skew between related clock outputs. measured at v dd /2. ? ? 250 ps note 4. skew and phase alignment is guaranteed within all ssclk outputs and within both refout outputs. all ssclk outputs are related , and all reout outputs are related, but ssclk and refout outputs are not related to each other. [+] feedback
cy25200 document number: 38-07633 rev. *h page 11 of 15 some product offerings are factory progra mmed customer specific devi ces with customized part numbe rs. the possible configura- tions table shows the available device types, but not complete pa rt numbers. contact your local cypress fae or sales representa tive for more information. possible configurations ordering code definitions ordering information ordering code package type programming operating temperature range cy25200kfzxc 16-pin tssop (pb-free) field commercial, 0 to 70 ? c cy25200kfzxct 16-pin tssop ? tape and reel (pb-free) field commercial, 0 to 70 ? c PROGRAMMER cy3672-usb PROGRAMMER for field programmable devices n/a n/a cy3695 cy22050/cy22150/cy25200 socket adapter for cy3672-usb n/a n/a ordering code [5] package type programming operating temperature range cy25200k-zxcxxxw 16-pin tssop (pb-fr ee) factory commercial, 0 to 70 ? c cy25200k-zxcxxxwt 16-pin tssop ? tape and reel (pb-free) factory commercial, 0 to 70 ? c t = tape and reel; blank = tube custom configuration code (f actory programmed device only) temperature: c or i or blank; c = commercial; i = industrial x = pb-free package package: z = tssop; s or blank = soic programming: f = field programm able; blank = factory programmed device part number company id: cy = cypress 25200k cy (z) x (t) (f) (c) (?xxx) table 5. 16-pin tssop package characteristics parameter name value unit ? ja theta ja 115 ? c/w note 5. ?xxx? denotes a specific device configur ation, and is referred to as the ?dash num ber?. ?w? denotes the configuration revision . [+] feedback
cy25200 document number: 38-07633 rev. *h page 12 of 15 package drawing and dimensions figure 8. 16-pin tssop 4.40 mm body zz16 51-85091 *c [+] feedback
cy25200 document number: 38-07633 rev. *h page 13 of 15 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor emc electro magnetic compatibility emi electro magnetic interference fae field application engineer oe output enable osc oscillator pll phase locked loop ssc spread spectrum clock sscg spread spectrum clock generator tssop thin shrunk small outline package symbol unit of measure c degree celsius ? ohms k ? kilo ohms khz kilo hertz mhz mega hertz a micro amperes ms milli seconds mw milli watts ns nano seconds % percent pf pico farad ps picoseconds vvolts [+] feedback
cy25200 document number: 38-07633 rev. *h page 14 of 15 document history page document title: cy25200 programmable spread spectrum clock generator for emi reduction document number: 38-07633 rev. ecn no. orig. of change submission date description of change ** 204243 rgl see ecn new data sheet *a 220043 rgl see ecn minor change: corrected letter a ssignment in the ordering info for pb free. *b 267832 rgl see ecn added field programmable devices and functionality *c 291094 rgl see ecn added t skew spec. and footnote *d 1821908 dpf/aesa see ecn corrected fssclk-low volt age specification on page 7 for ssclk5/6 to ssclk1/2/3/4, as ssclk5/6 output does not operate at low voltage. deleted tccj4 on page 8 for the same reason as above *e 2442066 kvm/aesa see ecn updated template. added note ?not recommended for new designs.? added part number cy25200kzxc_xxxw, cy25200kzxc_xxxwt, cy25200kfzxc in ordering information table. changed package name to zz16. *f 2758387 kvm/aesa 09/01/2009 extensive text edits replaced benefits column on page 1 with description revised ta b l e 2 and ta b l e 3 for clarity revised the modulation frequency paragraph to align with actual software options and to delete ment ion of custom frequencies corrected 3.3v i ol and i oh values, filled in missing units in ac electrical table revised t skew footnote for clarity removed specific pd# and oe pin nos. from parameters t stp , t oe1 and t oe2 standardized timing parameter names to upper case corrected part numbers in ordering information table removed part number cy25200fzxct added part number cy25200kfzxct replaced cy3672 and cy3672-prg with cy3672-usb *g 2897246 kvm 03/22/10 removed inactive parts from ordering information table. added note regarding possible configurations in ordering information section. removed note 6. added possible configurations table. updated package drawing and dimensions . *h 3103982 bash 07/12/2010 added ordering code definitions . updated package drawing and dimensions . added acronyms and units of measure . minor edits and updated in new template. [+] feedback
document number: 38-07633 rev. *h revised december 7, 2010 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy25200 ? cypress semiconductor corporation, 2004-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at www.cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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